Generally, as the size of memory increases, the number of cells in the memory also increases and parameters, such as time delays, parasitic capacitances, etc., become significant. These parameters, in turn, affect the overall performance of the memory. In order to improve the memory performance, it is a common practice to segment the memory. For example, in the hierarchical memory architecture, such as a multi-banked memory architecture, a single block of memory is virtually divided into multiple memory banks or sub-arrays. Each memory bank includes a number of memory cells arranged in rows and columns called word lines and bit lines, respectively. In addition, each memory bank is associated with a local clock generation circuitry and a local write circuitry, collectively referred to as local input and output circuitry (LIOC). The LIOC includes a system of write data buses. LIOCs of different memory banks interact with a global input and output circuitry (GIOC) for a bi-directional transfer of data between the LIOCs and the GIOC. The GIOC includes a global write circuitry and a global clock generation circuitry. Similar to the LIOCs, the GIOC also includes global data buses.
Typically, before performing a write operation, the global write circuitry of the GIOC is pre-charged to a level of supply voltage through a number of pull-up pre-charge devices. The pre-charge devices are associated with a number of global sub-write circuitries within the global write circuitry. The pull-up pre-charge devices of all the global sub-write circuitries are triggered even if only one global sub-write circuit is selected for the write operation. Furthermore, even though the data to be written (write-data) is to be transferred to only the LIOC of a selected memory bank, the LIOCs of several unselected memory banks also get un-necessarily triggered. This leads to high dynamic power consumption as the write-data is propagated from the GIOC to the LIOCs of several unselected memory banks as well.
Further, the write operation in the LIOC of a memory bank is inherently slow due to the large size of components, for example, logic gates of the GIOC. Therefore, to increase the speed of the write operation in an LIOC, the size of the pull-up pre-charge devices is considerably increased, thereby increasing peak current and dynamic power dissipation.
During the GIOC-LIOC communication, resetting of the GIOC is not initiated until the write operation is completed in the LIOC. In addition, the GIOC requires tuning of the pulse width of a global write clock signal in order to reset the write circuitry of the GIOC for different compiler ranges i.e., variable number of memory banks. Such tuning of the global write clock signal for a memory bank having large compiler range results in an extended clock cycle time of the global write clock signal even for a memory bank having a smaller compiler range. Due to this extended clock cycle time, the performance of the memory bank having smaller compiler range gets adversely affected.